1. Field of the Invention
This invention relates to integrated circuit packaging and more particularly to methods for analyzing laminate warpage in integrated circuit packaging.
2. Description of the Related Art
In recent years, organic laminates have become a popular choice in flip-chip packages as a way to reduce costs compared to conventional laminates. Organic laminates, however, are typically characterized by significant mismatch of the coefficient of thermal expansion (CTE) between layers. This mismatch creates significant differences in thermal expansion or contraction during the fabrication process, causing the laminate to warp. Among other consequences, this warpage makes it difficult to produce reliable solder interconnects between the organic laminate and a chip during the chip joining process.
Currently, manufacturers of organic laminates cannot easily produce substrates with a low coplanarity, especially in complex designs (e.g., laminates with a large number of build-up layers). The burden of producing reliable microelectronic packages currently resides with the packaging industry, which has to develop complex and expensive capping processes, for instance, to alleviate the laminate warpage problem. Although some process parameters may be modified to reduce laminate warpage during manufacture, laminate characteristics that contribute to warpage need to be understood properly in order to know which parameters to modify.
In view of the foregoing, what are needed are methods to effectively analyze warpage in organic laminates. Further needed are methods to understand which laminate characteristics are the primary contributors to warpage. Yet further needed are methods to determine which layers or groups of layers are the primary contributors to laminate warpage. Yet further needed are methods to determine how layer thicknesses contribute to laminate warpage.